The present invention relates to processes for reducing surface roughness of superconductor and semiconductor materials and more particularly, to processes for reducing the surface roughness of niobium nitride (NbN) and to superconductor integrated circuits formed on a ground plane of NbN.
Superconductor integrated circuits utilizing NbN ground plane have been developed which operate at 10 K. These circuits utilize a thick (500 nm) NbN ground plane layer disposed on thermally oxidized silicon wafers and trilayer Josephson junction for the active device. The thick NbN layer has a high surface roughness which prevents direct fabrication of trilayer devices on the top surface thereof as described below in more detail in conjunction with FIG. 2
Superconductive niobium nitrate integrated circuits having trilayer NbN/MgO/NbN devices have substantial high current density tunnel junctions ranging from 1000 A/cm2 to 5,000 A/cm2. See G. L. Kerber, et al., xe2x80x9cAn Improved NbN Integrated Circuit Process Featuring Thick NbN Ground Plane and Lower Parasitic Circuit Inductancesxe2x80x9d, IEEE Transactions on Applied Superconductivity, Vol 7, pp. 2638-2643 (June 1997). This publication is incorporated by reference herein in its entirety.
While the use of bias sputtered SiO2 effectively smooths the surface roughness of a NbN ground plane to enable the fabrication of high current density NbN/MgO/NbN trilayer devices over the thick NbN ground plane, there still exists a problem that this process produces NbN/MgO/NbN devices with unacceptably high inductance existing between the NbN/MgO/NbN trilayer devices and the ground plane which is the result of the layer of SiO2 spacing the NbN/MgO/NbN trilayer devices from the ground plane.
FIG. 1 illustrates a simplified cross section of a prior art trilayer NbN/MgO/NbN device in accordance with the foregoing publication and as described in the Assignee""s patent application Ser. Nos. 08/833,954 and 09/066,494 respectively filed on Oct. 20, 1997 and Jan. 13, 1998, and each entitled Low Inductance Superconductive Integrated Circuit and Method of Fabricating the Same which applications are incorporated herein by reference in their entirety. The trilayer device 10 has a NbN base electrode 12, a MgO tunnel barrier 14 of approximately 1 nm in thickness and a NbN counter electrode 16. Tunnel barriers of other materials such as AIN and oxidized metal may be used. The bias sputtered layer 18 of SiO2 has a top surface 22 having an unacceptable surface roughness preventing direct fabrication of the NbN/MgO/NbN trilayer devices 10 thereto on. The SiO2 layer 18 spaces the trilayer NbN/MgO/NbN devices from the unacceptably rough top surface 22 of the NbN ground plane 23. The unacceptable surface roughness of the top surface 22, which is described below in conjunction with FIG. 2, prevents the NbN/MgO/NbN trilayer devices 10 from being directly formed on the NbN ground plane 23. The contoured portion 24 of the base electrode 12, which connects the devices 10 to the NbN ground plane 23, adds parasitic inductance to the NbN/MgO/NbN integrated circuit which decreases the switching speed below that which may be achieved if the NbN/MgO/NbN trilayer was formed directly on surface 22. In FIG. 1, the trilayer devices 10 are spaced approximately 150 nm away from the ground plane 22 which spacing is sufficient to effectively prevent excessive leakage or even short circuits but results in the aforementioned increased parasitic inductance.
FIG. 2 illustrates a cross sectional view of a thick NbN ground plane 23 which has been prepared in accordance with the prior art discussed above. This ground plane is typically 500 nm in thickness and is characterized by a fine grain columnar structure. The surface roughness is on the order of 4 nm rms. The peak 30 to valley 32 roughness ranges typically from 15-20 nm. NbN surface roughness increases faster than the film thickness which makes it impossible to make a thick film NbN ground plane, which is known to reduce parasitic inductance, sufficiently smooth to permit direct fabrication of NbN/MgO/NbN trilayer devices 10 on the ground plane 23. This surface roughness is so great that either excessive leakage or short circuits would result if the trilayer devices 10 were fabricated directly on the NbN ground plane 23.
Etch back planarization is known which utilizes a polymer to fill rough semiconductor surfaces. The resultant product is not sufficiently smooth to permit fabrication of circuits requiring smoothness on the order of that required to permit NbN/MgO/NbN trilayer devices to be directly formed on a NbN ground plane.
Single crystal NbN can be made smooth but large scale fabrication useful for integrated circuits is difficult to achieve because of many surface defects which make the resultant NbN/MgO/NbN trilayer junctions inoperative.
Superconductor films of niobium titanium nitride have reduced surface roughness of approximately 1 nm. However, niobium titanium nitride is subject to high stress making it unusable for NbN/MgO/NbN trilayer devices having a ground plane for reducing parasitic inductance.
The invention is a process for reducing roughness of a surface of a superconductor and/or semiconductor material which has a preferred application of reducing the surface roughness of a NbN superconductor substrate functioning as a ground plane in superconductor Josephson junction-type integrated circuits and further to any trilayer superconductor integrated circuit having NbN/MgO/NbN trilayer devices formed on a thick NbN ground plane which has been processed to reduce surface roughness in accordance with the process of the present invention to permit direct fabrication of the trilayer devices on the ground plane.
A process for reducing roughness of a surface of a superconductor material having an undesirable surface roughness in accordance with the invention includes coating the surface with an oxide layer to fill the undesirable surface roughness and to produce an exposed oxide surface with a roughness less than the undesirable surface roughness of the superconductor material on which the coating is applied. The coating is preferably SiO2 which has been bias sputtered with a low frequency, such as 40 kHz, which produces a smooth oxide film having a surface roughness which is substantially less than the roughness of the NbN and may be less than 0.1 nm rms. Thereafter, the exposed oxide surface is etched to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface comprised of at least the superconductor material which has surface roughness less than the undesired surface roughness. The exposed etched surface may also comprise the oxide layer.
The etching is produced by an etching material which etches each of the oxide layer and the superconductor material at substantially the same rate (as close to 1:1 as possible) so that a surface roughness of the exposed surface is replicated on the exposed etched surface. As a result, the top surface of the superconductor material, which is preferably NbN, has a surface smoothness sufficient to permit Josephson junction trilayer devices such as NbN/MgO/NbN or NbN/ALAN/NbN devices to be formed directly on the NbN ground plane. The oxide layer is preferably SiO2 coated on the superconductor layer by sputtering. Preferably, the sputter deposition is bias sputtering (substrate is biased using low frequency such as 40 kHz) and the etching is dry etching. A preferred etching composition comprises a mixture of O2 and a gas containing C, H and a halogen with CHF3 being one preferred composition.
Trilayer-based superconductor integrated circuits formed directly on a substrate of NbN have reduced parasitic inductance consequent from eliminating the contoured portion 24 of base electrode 12 in the prior art of FIG. 1 to connect the trilayer devices to the thick NbN ground plane which produced unacceptably high parasitic inductance.
A trilayer-based superconductor integrated circuit formed on a thick NbN ground plane film in accordance with the invention includes a ground plane of NbN formed by the process of coating a surface of the NbN having an undesirable surface roughness with an oxide layer to fill the undesirable surface roughness and to produce an exposed oxide surface. Thereafter, the exposed oxide surface is etched to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the surface roughness and a portion of the surface of the NbN to produce an exposed etched surface comprised of the NbN which has a roughness less than the undesirable surface roughness. At least one trilayer device is formed on the ground plane of NbN each including a base electrode in surface contact with the exposed etched surface, a tunnel layer in surface contact with the base electrode, a counter electrode of NbN in surface contact with the top surface of the tunnel layer, and a wiring layer is in surface contact with a top surface of the counter electrode. Preferably, the exposed etched surface also comprises the oxide layer. The tunnel layer is preferably AlN or MgO. The etching of the substrate of NbN is performed with an etching material which etches each of the oxide layer and the superconductor material at substantially the same rate (1:1 is preferable) so that a surface roughness of the exposed oxide surface is replicated on the exposed etched surface. The oxide layer is preferably SiO2 coated on the superconductor layer with sputtering. Sputtering is preferably bias sputtering and is preferably low frequency, such as 40 kHz, and the etching is dry etching with the etching material preferably comprising a mixture of O2 and a gas containing C, H and halogen with a preferred composition being CHF3.
The integrated circuit further includes an interleaved oxide layer disposed in surface contact with the ground plane; and at least one additional trilayer device each having another base electrode of NbN electrically coupled to the ground plane and in surface contact with the interleaved oxide layer; another tunnel layer in surface contact with the another base electrode; another counter electrode of NbN in surface contact with another tunnel layer; and another wiring layer in surface contact with the another counter electrode.
A trilayer-based superconductor integrated circuit in accordance with the invention includes a ground plane substrate of NbN having a top surface having a roughness below 4 nm rms; and at least one trilayer device each including a base electrode of NbN in surface contact with the top surface, a tunnel layer in surface contact with the base electrode, a counter electrode of NbN in surface contact with the tunnel layer, and a wiring layer in surface contact with the counter electrode. The tunnel layer may be AlN or MgO. The integrated circuit further includes an interleaved oxide disposed in surface contact with the ground plane; and at least one additional trilayer device each having another base electrode of NbN electrically coupled to the ground plane and on top of the interleaved oxide layer, another counter electrode of NbN in surface contact with another tunnel layer, and another wiring layer in surface contact with another counter electrode. The oxide layer is preferable SiO2 and the tunnel layer preferably is MgO or AlN.
The resultant trilayer junctions have lower inductance and therefore perform better than the trilayer junctions fabricated on a smooth silicon dioxide surface in accordance with the prior art of FIG. 1.